The International Business Machines AP-101 is an avionics computer, used most notably in the U.S. Space Shuttle program, but also in the B-52 Stratofortress and F-15 Eagle, among others. When it was designed, it was a high-performance pipelined processor with core memory. As of 2004, its specifications are exceeded by many microprocessors. The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 IBM mainframes. It has 16 32-bit processor register, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the status register register, allowing a directly addressable memory range of 1mega locations. The original AP-101 was built using transistor-transistor logic integrated circuits. The main memory was originally core memory, but the AP-101S upgrade in the early 1990s used semiconductor memory. A shuttle uses five AP-101s as "general-purpose computers" (GPCs). Four operate in sync, for redundancy, while the fifth is a backup running software written independently. The shuttle software is written in HAL/S, a special-purpose high-level language, whereas AP-101s used by the US Air Force are mostly programmed in JOVIAL programming language. == References == *Norman, P. Glenn, IBM Corp. (1987). ''The new AP101S General-Purpose Computer (GPC) for the Space Shuttle''. IEEE Proceedings, Volume 75, pp.308–319, 01 March 1987. == External links == * [http://spaceflight.nasa.gov/shuttle/reference/shutref/orbiter/avionics/dps/gpc.html NASA description of shuttle GPCs] * [http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html NASA history of AP-101 development] Spacecraft components Avionics computers IBM hardware
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The International Business Machines AP-101 is an avionics computer, used most notably in the U.S. Space Shuttle program, but also in the B-52 Stratofortress and F-15 Eagle, among others. When it was designed, it was a high-performance pipelined processor with core memory. As of 2004, its specifications are exceeded by many microprocessors. The AP-101, being the top-of-the-line of the System/4 Pi range, shares its general architecture with the System/360 IBM mainframes. It has 16 32-bit processor register, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the status register register, allowing a directly addressable memory range of 1mega locations. The original AP-101 was built using transistor-transistor logic integrated circuits. The main memory was originally core memory, but the AP-101S upgrade in the early 1990s used semiconductor memory. A shuttle uses five AP-101s as "general-purpose computers" (GPCs). Four operate in sync, for redundancy, while the fifth is a backup running software written independently. The shuttle software is written in HAL/S, a special-purpose high-level language, whereas AP-101s used by the US Air Force are mostly programmed in JOVIAL programming language. == References == *Norman, P. Glenn, IBM Corp. (1987). ''The new AP101S General-Purpose Computer (GPC) for the Space Shuttle''. IEEE Proceedings, Volume 75, pp.308–319, 01 March 1987. == External links == * [http://spaceflight.nasa.gov/shuttle/reference/shutref/orbiter/avionics/dps/gpc.html NASA description of shuttle GPCs] * [http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html NASA history of AP-101 development] Spacecraft components Avionics computers IBM hardware
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